Microprocessors such as the PowerPC and x86 line have been the traditional work-horses of computing systems over the years. While they offer post-fabrication flexibility through software programmability, the demand for on-board autonomy-enabling applications has pushed the envelope of computation, complexity far beyond the reach of these processors. Application specific integrated circuits (ASICs), while being capable of meeting the computation demands of these algorithms, incur very high NRE (non-recurring engineering) costs and offer little to no flexibility for algorithmic changes in the post-deployment/fabrication phase. Field Programmable Gate Arrays (FPGAs) are gaining increasingly strong support in the computing community as the platform of choice for applications because they offer the best of both ASIC and microprocessor worlds. Today's state-of-the-art SRAM FPGAs have low cost, high capability and nearly-zero NRE. FPGA-based designs can be deployed as-is or converted to a low-cost structured ASIC.
In this disclosure, a novel FPGA-based architecture which performs iterative repair scheduling is presented. An overview of current designs and methodologies for supporting iterative repair, simulated annealing, and application-specific processors is presented. Details of the four-stage pipelined architecture are disclosed, followed by results and analysis that compares this new architecture with existing methods.
The design of an iterative repair processor leverages concepts from several different areas, including the development of the iterative repair algorithm itself development of heuristic search techniques, and application-specific hardware implementations of these techniques.